? semiconductor components industries, llc, 2012 april, 2012 ? rev. 2 1 publication order number: esd7104/d esd7104 transient voltage suppressors low capacitance esd protection for high speed data the esd7104 transient voltage suppressor is designed to protect high speed data lines from esd. ultra ? low capacitance and low esd clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. the flow ? through style package allows for easy pcb layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as usb 3.0 and hdmi. features ? low capacitance (0.3 pf typical, i/o to gnd) ? low esd clamping voltage ? protection for the following iec standards: iec 61000 ? 4 ? 2 (level 4) ? ul flammability rating of 94 v ? 0 ? this is a pb ? free device typical applications ? usb 3.0 ? esata 3.0 ? thunderbolt (light peak) ? hdmi 1.3/1.4 ? display port maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j ? 55 to +125 c storage temperature range t stg ? 55 to +150 c lead solder temperature ? maximum (10 seconds) t l 260 c iec 61000 ? 4 ? 2 contact (esd) iec 61000 ? 4 ? 2 air (esd) esd esd 15 15 kv kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. see application note and8308/d for further description of survivability specs. marking diagram device package shipping ordering information udfn10 case 517bb pin configuration and schematic http://onsemi.com ESD7104MUTAG udfn10 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 7m m 7m = specific device code (tbd) m = date code = pb ? free package i/o i/o i/o i/o gnd n/c n/c n/c n/c gnd 145 23 10 7 6 98 (note: microdot may be in either location) gnd pin 2 pin 4 pin 5 pin 1 = i/o i/o i/o i/o pin 3
esd7104 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm i/o pin to gnd 5.0 v breakdown voltage v br i t = 1 ma, i/o pin to gnd 5.5 v reverse leakage current i r v rwm = 5 v, i/o pin to gnd 1.0 a clamping voltage (note 1) v c i pp = 1 a, i/o pin to gnd (8 x 20 s pulse) 10 v clamping voltage (note 2) v c iec61000 ? 4 ? 2, 8 kv contact see figures 1 and 2 v clamping voltage (note 3) v c i pp = 8 a i pp = 16 a 14.1 19.5 v junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins 0.2 0.3 pf junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins and gnd 0.3 0.35 pf 1. surge current waveform per figure 5. 2. for test procedure see figures 3 and 4 and application note and8307/d. 3. ansi/esd stm5.5.1 ? 2008 electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. figure 1. iec61000 ? 4 ? 2 +8 kv contact clamping voltage figure 2. iec61000 ? 4 ? 2 ? 8 kv contact clamping voltage time (ns) 120 100 80 60 40 20 0 ? 20 ? 10 0 10 20 30 40 50 60 voltage (v) 140 70 80 time (ns) 120 100 80 60 40 20 0 ? 20 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 voltage (v) 140 0 10
esd7104 http://onsemi.com 3 iec 61000 ? 4 ? 2 spec. level test voltage (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000 ? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 3. iec61000 ? 4 ? 2 spec figure 4. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d. figure 5. 8 x 20 s pulse waveform 100 90 80 70 60 50 40 30 20 10 0 020406080 t, time ( s) % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 8 s peak value i rsm @ 8 s half value i rsm /2 @ 20 s
esd7104 http://onsemi.com 4 figure 6. positive tlp i ? v curve figure 7. negative tlp i ? v curve current (a) voltage (v) current (a) voltage (v) 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 16 18 20 22 18 20 0 ? 2 ? 4 ? 6 ? 8 ? 10 ? 12 ? 14 ? 16 ? 18 ? 20 ? 22 22 24 ? 14 ? 12 ? 10 ? 8 ? 6 ? 4 ? 2 0 ? 16 ? 18 ? 20 ? 22 ? 2 4 transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i ? v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 8. tlp i ? v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 9 where an 8 kv iec 61000 ? 4 ? 2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i ? v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. figure 8. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 9. comparison between 8 kv iec 61000 ? 4 ? 2 and 8 a and 16 a tlp waveforms
esd7104 http://onsemi.com 5 with esd7104 without esd figure 10. usb3.0 eye diagram with and without esd7104. 5.0 gb/s, 400 mv pp with esd7104 without esd figure 11. hdmi1.4 eye diagram with and without esd7104. 3.4 gb/s, 400 mv pp with esd7104 without esd figure 12. esata3.0 eye diagram with and without esd7104. 6 gb/s, 400 mv pp
esd7104 http://onsemi.com 6 figure 13. esd7104 insertion loss ? 10 ? 8 ? 6 ? 4 ? 2 0 2 4 1.e+06 1.e+07 1.e+08 1.e+09 1.e+10 esd7104 io ? gnd frequency (hz) s21 insertion loss (db)
esd7104 http://onsemi.com 7 figure 14. usb3.0 standard a connector layout diagram vbus stda_sstx+ d ? stda_sstx ? d+ gnd_drain gnd stda_ssrx+ stda_ssrx ? usb 3.0 type a connector esd7104 esd7l5.0 figure 15. usb3.0 micro b connector layout diagram d ? vbus id d+ micb_sstx ? gnd gnd_drain micb_sstx+ micb_ssrx ? usb 3.0 micro b connector micb_ssrx+ esd7104 esd7104
esd7104 http://onsemi.com 8 figure 16. hdmi layout diagram hdmi type a connector scl 5v cec gnd d0 ? gnd d0+ d2 ? d2+ hpd (and hec_dat ? hdmi1.4) gnd sda clk ? clk+ gnd d1+ d1 ? gnd n/c (or hec_dat ? hdmi1.4) esd7104 esd7104 nup4114 a ? a+ gnd b ? b+ gnd gnd e s ata connector esd7104 figure 17. esata layout diagram
esd7104 http://onsemi.com 9 package dimensions udfn10 2.5x1, 0.5p case 517bb issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal. c seating plane d b e 0.10 c a3 a a1 2x 2x 0.10 c dim a min millimeters 0.45 a1 0.00 a3 0.13 ref b 0.15 d 2.50 bsc b2 0.35 e 1.00 bsc e 0.50 bsc pin one reference 0.08 c 0.10 c 10x a 0.10 c note 3 l e b2 b b 5 6 8x 1 10 10x 0.05 c 0.30 l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 0.45 0.50 dimensions: millimeters 1.30 pitch 0.25 10x 0.55 0.05 0.25 0.45 0.40 max ??? a1 a3 detail b mold cmpd exposed cu optional construction l1 detail a l optional constructions l --- l1 0.05 top view side view bottom view detail b detail a outline package a 2x recommended 2x 8x on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. esd7104/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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